1. Field of the Invention
The present invention relates to phase lock loops, more particularly to phase lock loops having both a wide-band mode and a narrow-band mode of operation.
2. State of the Art
Practically all modern signal generators and radio communications equipment use digital frequency synthesizers based on the phase-locked loop (PLL). The realization of the PLL in an integrated circuit has led to the widespread adoption of inexpensive frequency synthesizers. In its application to frequency synthesis (as opposed to signal detection), the input signal-to-noise ratio of the PLL is high, and the PLL serves to lock the output frequency on a multiple of the input frequency.
A PLL consists generally of three parts: a reference frequency input portion, a loop filter portion, and a voltage-controlled oscillator (VCO) portion. The reference frequency portion includes a phase comparator and may include a frequency divider (which may be programmable). The phase comparator compares an output signal of the PLL with the reference frequency itself or the reference frequency divided down, thereby producing an error signal. The loop filter filters the error signal to produce a control signal that is applied to the VCO. During proper operation, the control signal drives the VCO in the proper direction so as to cause the error signal to be driven to zero or nearly zero.
PLLs generally operate in two different modes: acquisition during which the PLL locks onto a particular frequency, and tracking, during which the PLL ensures that it remains locked. Both fast acquisition and accurate tracking are important design objectives. Unfortunately, these design objectives are, in general, conflicting. For fast acquisition, a wide loop bandwidth is desired. For accurate tracking, in the presence of modulation, a narrow loop bandwidth is desired. The disparity between the desired bandwidths in the two modes may be considerable. In cellular applications, for example, when changing channels, a wide loop bandwidth is desired to accomplish the frequency change as quickly as possible. When operating on a single channel, voice data having low frequency content is modulated onto a carrier signal. The PLL attempts in effect to cancel the modulation, which appears to the PLL as frequency drift. To accomplish slow modulation, therefore, a very narrow loop bandwidth is desired, such that the modulation is accomplished outside the PLL bandwidth.
One proposal, xe2x80x9cA Fast Locking Scheme for PLL Frequency Synthesizersxe2x80x9d, National Semiconductor Application Note 1000 (1995), has been to, in narrow-band mode, open the loop entirely during short modulation bursts and to close the loop when modulation is not applied. This approach assumes that, if the loop is opened for only short periods at a time, the drift that may occur during open-loop operation will not be substantial. This solution may be acceptable under certain limited conditions but is not generally applicable.
In the case of a current-mode charge pump loop filter, the required change in current gain is proportional to the square of the required change in bandwidth. Referring more particularly to FIG. 1, a portion of a PLL is shown, including a loop filter 101 and a VCO 111. A charge pump 105 has a first xe2x80x9cpump-upxe2x80x9d current source 107 connected to inject current into circuit node A, and a second xe2x80x9cpump-downxe2x80x9d current source 109 connected to withdraw current from the same node. The pump-up current source 107 is connected to a positive supply voltage V+, and the pump-down current source 109 is connected to a negative supply voltage Vxe2x88x92. Besides the charge pump 105, there is also connected to node A a capacitor C1 connected to ground and the series combination of a resistor R1 and capacitor C2, connected to ground. A tuning voltage VT is produced at node A and is input to the VCO 111 to control the frequency of oscillation of the VCO.
The loop bandwidth of the circuit of FIG. 1 may be changed by changing the values of one or both of the capacitors (C1, C2), such that they charge more slowly or more quickly. Changing the values of the capacitors usually requires some form of switching. However, it is also important not to disturb the charge on the capacitors. Switching usually introduces undesirable transients. A preferable way of changing the loop bandwidth, then, is to vary the magnitude of the currents supplied by the current sources (107, 109). To switch from wide to narrow bandwidth, for example, instead of switching in additional capacitors to make the capacitance larger, the current gain would be altered to make the currents smaller.
One known circuit that follows the foregoing approach is shown in FIG. 2 and described in U.S. Pat. No. 5,831,483, incorporated herein by reference. The VCO 1 is supplied with a control signal Vc to produce an oscillation signal fo having an oscillation frequency that corresponds to the supplied control signal Vc. The variable frequency-divider 2 is supplied with the oscillation signal fo to produce a frequency-divided signal fv, while the reference signal generator 3 generates a reference signal fr. The frequency-phase comparator 4 is supplied with the frequency-divided signal fv and the reference signal fr to compare frequency/phases between both signals. The frequency-phase comparator 4 outputs a corresponding error signal, up signal or down signal, as a result of the comparison. The charge pump 10 supplies a charge pump signal cp to the loop filter 6 in response to input of the error signal. In other words, the charge pump 10 supplies the loop filter 6 with a charge output when the up signal is active or a discharge output when the down signal is active. The loop filter 6 integrates and smooth the received charge pump signal cp to produce the control signal Vc. The output of the loop filter 6, i.e., the control signal Vc, is fed back to the VCO 1, thus forming the PLL.
When changing frequency, the current-flow control circuit 11 increases the amount of charge/discharge current flow of the charge pump 10 to raise the loop gain, so that the pull-in time (lock-up time) is shortened. After changing the frequency, it reduces the output current of the charge pump 10 so as to secure a stable circuit action.
The foregoing general type of PLL circuit is susceptible to many different realizations. The present invention relates to particularly advantageous realizations of the same.
The present invention, generally speaking, provides for bandwidth switching of a PLL in a simple, effective manner. In accordance with one embodiment, a phase lock loop includes a controlled oscillator responsive to a control voltage for producing an output signal of some output frequency; a comparator responsive to a feedback signal derived from the output signal and to a reference signal for producing at least one error signal; a charge pump circuit including multiple pairs of unidirectional current sources (or, alternatively, multiple bidirectional current sources); a control circuit responsive to a control signal for activating one or more pairs of unidirectional current sources, at the same time deactivating one or more pairs of unidirectional current sources; and a loop filter responsive to the multiple pairs of unidirectional current sources for producing the control voltage governing the output frequency. In accordance with another embodiment of the invention, a phase lock loop includes a controlled oscillator responsive to a control voltage for producing an output signal of some output frequency; a comparator responsive to a feedback signal derived from the output signal and to a reference signal for producing at least one error signal; a charge pump circuit coupled to a loop filter at at least one circuit node, the loop filter being responsive to at least the charge pump circuit for producing the control voltage; a logic driver coupled to said circuit node through a resistor; and a control circuit responsive to at least one control signal for controlling a state of the logic driver. Preferably, the logic driver is a tri-state device.